As manufacturing process of a semiconductor integrated circuit device, including a semiconductor memory device, becomes more refined, defective memory cells in a memory device are more frequently replaced with redundancy memory cells, so that it becomes necessary to increase the number of redundancy memory cells. If the number of redundancy memory cells increases, however, a chip area increases, as well. It is, therefore, of importance to elaborate a more effective method for replacing a defective memory cell with a redundancy memory cell and to enhance efficiency. According to conventional techniques, a group of redundancy memory cells is individually allotted to each of memory cell groups to be read or written through different buses, respectively.
FIG. 6 is a block diagram showing a structure of a semiconductor memory device according to a conventional technique. In FIG. 6, a semiconductor memory device comprises DQ1 normal cell array 100, DQ2 normal cell array 200, DQ1R redundancy cell array 110, and DQ2R redundancy cell array 210. In this case, symbols DQ1i/o and DQ2i/o designate input/output terminals. The DQ1 normal cell array 100 and DQ1R redundancy cell array 110 correspond to the input/output terminal DQ1i/o. Also, the DQ2 normal cell array 200 and DQ2R redundancy cell array 210 correspond to the input/output terminal DQ2i/o. In the semiconductor memory device according to the conventional technique, one redundancy cell array is provided for each normal cell array.
The semiconductor memory device of FIG. 6 further comprises an input/output circuit 41, a data amplifier 33, a write amplifier 35, a column decoder 37, an input/output circuit 42, a data amplifier 34, a write amplifier 36, a redundancy column decoder 40, a column decoder 38 and a redundancy control circuit 43.
FIG. 7 is a timing chart for describing the operation of the conventional semiconductor memory device shown in FIG. 6. In the first to fourth clock cycles, wherein each clock cycle is determined by an internal clock signal ICLK produced from an external clock signal, potential level of column switch lines YSW11.about.YSW1n and column switch lines YSW21.about.YSW2n change in accordance with inputted column addresses YADD, as shown in FIG. 7. In each cycle, potential level of one of each of a plurality of column switch lines inputted to the DQ1 normal cell array 100 and DQ2 normal cell array 200, respectively, is activated. In sense amplifiers connected to the activated column switch line, data is transmitted to and from local input/output buses LIOBUS11.about.LIOBUS1m in accordance with data signal amplified by the sense amplifiers.
Assuming that the column address YADD provided in the second cycle is a column address of a column including one or more defective cells in the DQ1 normal cell array, DQ1R column redundancy selection signal YREDDQ1 becomes an active level (H). Also, assuming that the column address YADD provided in the fourth cycle is a column address of a column including one or more defective cells in the DQ2 normal cell array, DQ2R column redundancy selection signal YREDDQ2 becomes an active level (H).
In this case, in the second cycle, a redundancy column switch line RYSW1 is selected in response to the DQ1R column redundancy selection signal YREDDQ1, and data is transmitted to and from redundancy local input/output buses LIOBUS11.about.LIOBUS1m in sense amplifiers connected to the redundancy column switch line RYSW1 in accordance with data signals amplified by the sense amplifiers. In the fourth cycle, a redundancy column switch line RYSW2 is selected in response to the DQ2 column redundancy selection signal YREDDQ2, and data is transmitted to and from local input/output buses LIOBUS21.about.LIOBUS2m in sense amplifiers connected to the redundancy column switch line RYSW2 in accordance with data signals amplified by the sense amplifiers.
Accordingly, the data of global input/output buses GIOBUS1 and GIOBUS2 are transmitted to read/write buses RWBUS1 and RWBUS2, respectively in the first cycle; the data of a redundancy global input/output bus RGIOBUS1 and that of the global input/output bus GIOBUS2 are transmitted thereto, respectively in the second cycle; the data of the global input/output buses GIOBUS1 and GIOBUS2 are transmitted thereto, respectively in the third cycle; and the data of the global input/output bus GIBUS1 and that of the redundancy input/output bus RGIBUS2 are transmitted thereto, respectively in the fourth cycle.
According to the conventional technique, different redundancy memory cell groups are allotted to memory cell groups to be read or written through different buses, respectively. Owing to this, the conventional technique has a disadvantage in that probability of relief greatly decreases if the number of defective memory cells increase in at least one of the memory cell groups.